Synchronous random access memories such as a synchronous dynamic random access memories (SDRAMs) and a synchronous graphic random access memories (SGRAMs) are designed to operate in a synchronous memory system. Thus, all input and output signals, with the exception of a clock enable signal during power down and self refresh modes, are synchronized to an active edge of a system clock.
SDRAMs offer substantial advances in dynamic memory operating performance. For example, some SDRAMs are capable of synchronously providing burst data in a burst mode at a high-speed data rate by automatically generating a column address to address a memory array of storage cells organized in rows and columns for storing data within the SDRAM. In addition, if the SDRAM includes two or more banks of memory arrays, the SDRAM preferably permits interleaving between the two or more banks to hide precharging time. SGRAMs differ from SDRAMs by providing certain column block write functions and masked write or write-per-bit functions to accommodate high-performance graphics applications.
In an asynchronous DRAM, once row and column addresses are issued to the DRAM and a row address strobe signal and column address strobe signal are deactivated, the DRAM's memory is precharged and available for another access. Another row cannot be accessed in the DRAM array, however, until the previous row access is completed.
By contrast, a SDRAM requires separate commands for accessing and precharging a row of storage cells in the SDRAM memory array. Once row and column addresses are provided to a SDRAM in a SDRAM having multiple bank memory array's, a bank memory array which is accessed remains active. An internally generated row address strobe remains active and the selected row is open until a PRECHARGE command deactivates and recharges the selected row of the memory array.
In a SDRAM, a transfer operation involves performing a PRECHARGE command operation to deactivate and recharge a previously accessed bank memory array, performing an ACTIVE command operation to register the row address and activate the bank memory array to be accessed in the transfer operation, and performing the transfer READ or WRITE command to register the column address and initiate a burst cycle.
Read latency, such as one, two, or three clock cycles, is typically a programmable feature of SDRAMs and SGRAMs which guarantees which clock the data will be available, regardless of clock rate. Data can be made available on an output up to one clock less than the read latency, depending on the frequency of the system clock. In the art of memory design, read latency is sometimes referred to as column address strobe (CAS) latency.
In current SDRAMs and SGRAMs, when a write burst operation is followed by a READ command, a NOP command must be asserted during the transferring of the last data set of the burst write operation prior to issuing the READ command. There is a need to speed up the transition from a burst WRITE operation to a READ operation for certain higher read latencies required to accommodate systems employing SDRAMs or SCRAMs, which operate with faster clock frequencies.